Tegra186: mce: enable LATIC for chip verification

This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.

LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
used for various measurements relevant ot particular locations in
Silicon. They are small counters which can be polled to determine
how fast a particular location in the Silicon is.

Original change by Guy Sotomayor <[email protected]>

Change-Id: Ifb49b8863a009d4cdd5d1ba38a23b5374500a4b3
Signed-off-by: Varun Wadekar <[email protected]>

diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
index 7078b8bb2c9a8f65b629c49edd8133b8b7abc04d..825f81ff24a7175c9fd9b3435f268fcc6fec2ac3 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
@@ -94,6 +94,7 @@ typedef enum mce_cmd {
        MCE_CMD_ENUM_WRITE_MCA,
        MCE_CMD_ROC_FLUSH_CACHE,
        MCE_CMD_ROC_CLEAN_CACHE,
+       MCE_CMD_ENABLE_LATIC,
        MCE_CMD_IS_CCX_ALLOWED = 0xFE,
        MCE_CMD_MAX = 0xFF,
 } mce_cmd_t;

diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 745b6f4e563c1dca0216b7c558ae900b6ebd70c8..d105e36e39ee6d903f59d206cb461db4dd4ca0d3 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -356,6 +356,24 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
 
                break;
 
+#if ENABLE_CHIP_VERIFICATION_HARNESS
+       case MCE_CMD_ENABLE_LATIC:
+               /*
+                * This call is not for production use. The constant value,
+                * 0xFFFF0000, is specific to allowing for enabling LATIC on
+                * pre-production parts for the chip verification harness.
+                *
+                * Enabling LATIC allows S/W to read the MINI ISPs in the
+                * CCPLEX. The ISMs are used for various measurements relevant
+                * to particular locations in the Silicon. They are small
+                * counters which can be polled to determine how fast a
+                * particular location in the Silicon is.
+                */
+               ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(),
+                       0xFFFF0000);
+
+               break;
+#endif
        default:
                ERROR("unknown MCE command (%d)\n", cmd);
                return EINVAL;

diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index fabab0185ddc665ba1308fa5e2f8ce11f5eb086a..c7a2c416761816fa2d951efa0712e219f0e994ec 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -64,6 +64,7 @@ extern uint32_t tegra186_system_powerdn_state;
 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA               0x82FFFF0D
 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE              0x82FFFF0E
 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE              0x82FFFF0F
+#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC                 0x82FFFF10
 
 /*******************************************************************************
  * This function is responsible for handling all T186 SiP calls
@@ -100,6 +101,7 @@ int plat_sip_handler(uint32_t smc_fid,
        case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
        case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
        case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
+       case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
 
                /* clean up the high bits */
                smc_fid &= MCE_CMD_MASK;

diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index 0387a0a894851ef99c80108f3374d9ed90b29588..4a4d9bbda3b083ba5c9c7d34d835121200f14432 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -32,6 +32,9 @@
 ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS        := 1
 $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
 
+ENABLE_CHIP_VERIFICATION_HARNESS       := 0
+$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
+
 # platform settings
 TZDRAM_BASE                            := 0x30000000
 $(eval $(call add_define,TZDRAM_BASE))